ASIC Silicon Design Engineer
Job Summary
Job Description
This role involves designing custom silicon solutions for Google's direct-to-consumer products. Responsibilities include RTL development (Verilog, System Verilog) and debugging simulations; defining microarchitecture details; performing RTL quality checks (Lint, CDC, Synthesis, UPF); participating in synthesis, timing/power estimation, and FPGA/silicon bring-up; collaborating with teams to develop optimized interconnect blocks and subsystems; and ensuring specification adherence. The ideal candidate possesses experience with digital design in ASIC, RTL design using Verilog/System Verilog, ARM-based SoCs, and ASIC methodology. Proficiency in scripting languages like Python is also essential.
Must have:
- RTL design (Verilog/System Verilog)
- ASIC digital design experience
- ARM-based SoCs experience
- Scripting (Python/Perl)
- ASIC methodology knowledge
Good to have:
- Master's/PhD in EE/CS
- AMBA protocols experience
- RTL quality checks (Lint, CDC, RDC)
- Low power estimation & timing closure
- 2+ years ASIC design experience
5 skills required
Job Details
Minimum qualifications:
- Bachelor’s degree in Electrical or Computer Engineering, or equivalent practical experience is required.
- Experience with digital design in ASIC.
- Experience with a scripting language like Python or Perl.
- Experience with RTL design utilizing Verilog/System Verilog is necessary.
- Experience with ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
- 2 years of experience with digital design in ASIC.
- Experience with AMBA protocols.
- Experience with a scripting language like Python.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
- Experience with methodologies for low power estimation, timing closure, synthesis.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Demonstrate proficiency in RTL development (Verilog, System Verilog) and debugging functional/performance simulations.
- Define microarchitecture details including interface protocols, block diagrams and data flow.
- Perform RTL quality checks such as Lint, CDC, Synthesis, and UPF checks.
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.
- Collaborate within a team to develop and deliver optimized interconnect blocks and subsystems. And coordinate with architecture, design verification, and implementation teams to ensure specification adherence.
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