ASIC SoC Design Engineer

As an ASIC RTL engineer, you'll contribute to sub-system and chip-level integration, including task planning, code and design reviews. You'll collaborate with the architecture team to develop implementation strategies meeting quality, schedule, and power performance area goals. You'll interact with subsystem teams, plan SOC milestones, and implement quality checks. Collaboration with verification, design for test, physical design, emulation, and software teams is crucial for design decisions and project status updates. The role involves RTL coding using Verilog or SystemVerilog, experience in high-performance design, multi-power domains with clocking, and familiarity with ASIC design methodologies (Lint, CDC/RDC, Synthesis, DFT, ATPG/Memory BIST, UPF, Low Power Optimization/Estimation). Domain knowledge in areas like Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and PinMux is beneficial.