Associate III - VLSI-Memory Layout-SV
Job Summary
Job Description
- Memory Layout
- Layout Design
- Cadence Tools
- Memory Compiler
- IR/EM Issues
- DFM Guidelines
- Physical Verification
- Cross Functional
1 skill required
Job Details
About the job
Memory Layout
Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.
Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
Good handle on IR/EM related issues in memory layouts.
Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
Experience & or strong interest in memory compilers developed.
Excellent and demonstrated team player with ability to work with external customers and in cross functional teams
Skills
Memory Layout,Layout Design,Experience in memory compilers
Desired Skills and Experience
Memory Layout,Layout Design,Experience in memory compilersSimilar Jobs
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About The Company
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
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