Design Verification Engineer, Machine Learning, Silicon

This role involves verifying complex digital design blocks for machine learning silicon solutions at Google. Responsibilities include planning verification, creating and enhancing constrained random verification environments using SystemVerilog and UVM (or formal verification with SVA), identifying and writing coverage measures, debugging tests with design engineers, and closing coverage to ensure design correctness. The ideal candidate will have extensive experience in digital logic verification using SystemVerilog for FPGAs and ASICs, experience with verification methodologies (VMM, OVM, UVM), and familiarity with machine learning applications. The position requires collaborating with design engineers to identify important verification scenarios and contribute to the development of custom silicon solutions for Google's direct-to-consumer products.