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Manager II, Silicon Digital Design

California, United States (On-site)

Manager II, Silicon Digital Design

6 Days ago • 8-12 Years • Research & Development

About the job

5 skills required for this role

Add these skills to join the top 1% applicants for this job

python

perl

fpga

innovation

cross-functional

Job Description

Lead a team of engineers in designing custom silicon solutions for Google's consumer products. Responsibilities include setting team priorities, providing performance feedback and coaching, and leading technical design efforts. This role requires expertise in digital logic design, RTL design using Verilog/SystemVerilog, logic synthesis, low-power design, and scripting languages (Perl/Python). Collaboration with cross-functional teams (verification, DFT, physical design, software) is crucial. The ideal candidate will have strong experience in ASIC design methodologies and a deep understanding of processor cores, buses, and other relevant architectural components. The position involves architecture definition, die area estimation, power optimization, and performance enhancements.

Must have:

8+ years digital logic design experience
RTL design (Verilog/SystemVerilog)
4+ years people management experience
Logic synthesis & low-power techniques
Scripting (Perl/Python)
Lead and mentor engineering teams

Good to have:

Master's/PhD in relevant field
ASIC design methodologies
Processor Core, Bus/Fabric/NoC knowledge
ASIC Verification, DFT, synthesis, STA, Physical Design knowledge
FPGA and emulation platform experience

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
4 years of experience in people management, developing employees.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Experience with a scripting language like Perl or Python.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
Domain knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.
Knowledge of ASIC Verification, DFT, synthesis, STA, or Physical Design.
Knowledge of high performance and low-power design techniques.
Knowledge of FPGA and emulation platforms.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Lead a team of individuals; set and communicate individual and team priorities that support organizational goals. Meet regularly with individuals to discuss performance and development, and provide feedback and coaching.
Provide technical leadership to engineers and model best design practices (i.e. micro-architecture specifications, design reviews, code reviews, design methodology, etc.)
Participate with architecture and system design teams in architecture definition,die area estimation, power optimization and performance enhancements
Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

View Full Job Description

$177.0K - $266.0K/yr (Outscal est.)

$221.5K/yr avg.

Mountain View, California, United States

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.