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RTL(ASIC Design) Engineer

Karnataka, India (On-site)

RTL(ASIC Design) Engineer

2 Months ago • 5-10 Years • Research & Development

About the job

2 skills required for this role

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unity

innovation

Job Description

Marvell seeks an RTL (ASIC Design) Engineer with 5+ years of experience in micro-architecture, RTL coding, and pre-silicon verification. You'll work with the Architecture team, write specifications, and implement designs using best practices. Experience in leading design teams and mentoring junior engineers is a plus.

Must have:

RTL Coding
Micro-architecture
Pre-silicon Verification
Design Leadership

Good to have:

Post-silicon Validation
Project Management
Methodology Guidance
Mentorship

Perks:

Competitive Compensation
Great Benefits

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About the job

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Staff Engineer with Marvell, you’ll be a member of the CCS business group. This group focuses on custom, compute and storage solutions of Marvell. With the increased focus on the security of the products you will be involved in helping steer the SDL vision into on-going and future SoC's being worked on in the group. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

Work with the Architecture team as a design-team leader or member, to shape the micro-architecture of the IP block.

Write specifications for the relevant block, micro-architecture of one or more blocks.

Implement a specification using RTL coding techniques and best practices.

Work with the physical design teams.

Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug.

Work with the post-silicon validation teams in qualifying the device for production

Work with project manager to scope and assign tasks, including mentoring less experienced engineers

Work with multiple design centers and design groups to shape future methodology

Provide technical guidance and mentoring to junior engineers

What We're Looking For

Have a Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, Computer Science, or similar field with relevant exp of 5 to 10 years. Degree in mathematics, physics or other sciences may be considered provided adequate coursework in electronics was taken also or work experience has provided relevant knowledge since graduation.

Responsible engineer for at least one major sub-circuit block from architecture definition to fine tuning.

Identifies and proposes innovative solutions to enhance the design of at least one major block.

Participates in root cause investigation and silicon validation of the block.

Mentors and coaches new and/or less experienced team members.

Additional Compensation And Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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