Senior Silicon Validation Engineer
Job Summary
Job Description
- 5+ years experience with PLLs, PCIe, SerDes IPs
- Experience with lab equipment (scopes, analyzers)
- Proficiency in Python and Matlab
- SERDES debug and board design/debugging experience
- Thorough understanding of PCIe and SERDES
- PCIe compliance measurement experience
- Knowledge of Tx/Rx equalization techniques
- Experience with lab automation software
4 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience working with Phase-Locked Loops, PCIe, SerDes IPs.
- Experienced working with lab equipment such as Bidirectional Encoder Representations from Transformers (BERT), real-time scopes, Spectrum Analyzers, Vector Network Analyzers (VNA), or protocol analyzers.
- Experience with lab automation software such as Python, and Matlab.
- Experience with Serializer/Deserializer (SERDES) Debug.
- Experience of board design and debugging.
Preferred qualifications:
- Experience in PCIe compliance measurements using high-end equipment (e.g., Analyzer, Exerciser).
- Experience in lab equipment for PCIe testing (physical or protocol level).
- Knowledge of Tx/Rx equalization techniques and adaptation.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.As a PCIe Silicon Validation Engineer, you will take ownership on characterization of SERializer/DESerializer (SERDES) analog IPs provided by external vendors. Your will assure that the IP is meeting Google standards. You will work with different multi-functional teams within Silicon organization, as well as external vendors.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
- Write Inhouse tools/scripts to characterize the IP.
- Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
- Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
- Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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