SoC Physical Design Engineer, Implementation

1 Month ago • 4 Years + • Research & Development • $132,000 PA - $189,000 PA

Job Summary

Job Description

This SoC Physical Design Engineer role involves implementing innovative methodologies to improve performance, area, and power in ASIC design. Responsibilities include managing physical implementation for design partitions, collaborating with cross-functional teams, and developing all aspects of RTL2GDS implementation. The ideal candidate possesses expertise in synthesis/PnR tools (Genus, Innovus, DC, ICC), high-performance synthesis, PnR, sign-off convergence (STA and sign-off), and low-power design implementation (UPF/CPF, multi-voltage domains, power gating). Experience with scripting languages (TCI, Perl) and knowledge of computer architecture, Verilog/SystemVerilog, circuit design, device physics, and deep sub-micron technology are preferred.
Must have:
  • 4+ years Physical Design experience
  • Proficiency in synthesis/PnR tools
  • High-performance synthesis & sign-off expertise
  • ASIC RTL2GDS implementation
  • Cross-functional team collaboration
Good to have:
  • Low-power design implementation (UPF/CPF)
  • Scripting languages (TCI, Perl)
  • Knowledge of computer architecture, Verilog/SystemVerilog
  • Understanding of circuit design & device physics
Perks:
  • Bonus
  • Equity
  • Benefits

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience in Physical Design.
  • Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
  • Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off.

Preferred qualifications:

  • Experience with ASIC design flows and methodology of Physical design.
  • Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating.
  • Experience with scripting languages such as TCI, or Perl.
  • Knowledge of computer architecture, Verilog or SystemVerilog.
  • Understanding of Circuit design, device physics and deep sub-micron technology.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Define and implement innovative methodology schemes to improve Performance, Area and Power.
  • Develop all aspects of ASIC RTL2GDS implementation for designs.
  • Manage physical implementation for partitions.
  • Work with cross-functional teams to deliver results.

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