Junior Networking Design Verification Engineer
Job Summary
Job Description
- Bachelor's degree in relevant field
- Experience with verification components and environments
- RTL verification experience using SystemVerilog or Specman/E
- Verification planning, test execution, coverage closure
- Master's degree in EE or CS
- UVM experience
- Experience with scripting languages (Python, Perl, etc.)
- CPU implementation, assembly language, or compute SOCs experience
9 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Science.
- Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
- Experience with CPU implementation, assembly language, or compute SOCs.
About the job
As a Junior Networking Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Apply close coverage measures to identify verification holes and to show progress towards tape-out.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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