Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.

To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, for challenging low power designs, for 200MHz to several GHz big chips.

You will be working with internal and external customers for various design.

The job responsibility covers all of the key phases of implementation including RTL analysis, Synthesis, Design planning/optimization, timing verification, test insertion, physical design, CTS, STA, MMMC , timing closure and power optimization.

You will assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.

To play a leading role among other team members, while receive little instruction on routine and general assignments.

Position Requirements:        

A bachelor's degree is essential and 6+ years’ experience in IC design, electronic engineering or computer science applications.

Tape out experience in, 28nm or below technology, be insightful to make enhancement for design methodology/flow/script.

Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.

Good communication skill and self-manage attitude. Fluent English in Speaking.

Requires working knowledge of one or more programming languages, and effective communication and soft skills.

An MS degree and/or working experience in multi-nation IC design house is a plus.

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