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Senior SoC and IP Design Engineer, Google Cloud

Senior SoC and IP Design Engineer, Google Cloud

2 Weeks ago • 5 Years + • Research & Development

About the job

Summary

Google Cloud seeks a Senior SoC and IP Design Engineer to contribute to the development of custom silicon solutions for their direct-to-consumer products. Responsibilities include defining SoC/block level design documents, performing RTL development using Verilog/SystemVerilog, participating in synthesis, timing/power closure, and ASIC silicon bring-up. The role also involves test plan creation, coverage analysis, and collaboration with multi-disciplinary teams. The ideal candidate will have 5+ years of experience in digital logic design, RTL design, logic synthesis, and design verification. Experience with design sign-off tools and knowledge of high-performance/low-power design techniques are preferred.

4 skills required for this role

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level-design

python

perl

innovation

Must have:

5+ years experience in digital logic design
RTL design (Verilog/SystemVerilog)
Logic synthesis and verification
Design sign-off tools (Lint, CDC)
SoC/block level design documentation

Good to have:

Scripting (Python/Perl)
High-performance/low-power design
Assertion-based formal verification
SoC architecture knowledge
PCIe, UCIe, DDR, AXI, ARM processor domain knowledge

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Experience in logic design and debug with Design Verification (DV).
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).

Preferred qualifications:

Experience in scripting languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of System-on-a-Chip (SoC) architecture.
Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.