Memory Controller Verification Engineer
Job Summary
Job Description
Rivos is seeking Memory Controller design verification engineers to join their team in building high-performance memory interfaces. The role involves functional, performance, DFD, and DFT verification of DDR and HBM memory subsystem designs. Responsibilities include collaborating with architects and design teams, validating third-party IP integrations, developing test plans and testbenches, integrating VIPs, creating test stimulus and checkers in SystemVerilog/UVM, debugging, regression, and coverage closure. The engineer will also provide support for emulation and silicon bring-up teams and work with international teams.
Must have:
- Verify DDR/HBM memory subsystem design
- Knowledge of LPDDRx/DDRx/HBMx specifications
- Knowledge of DDR DFI specification
- Knowledge of RAS features for memory subsystems
Good to have:
- Work closely with architect and design team
- Work closely with 3rd party IP vendors
- Develop testplan and testbench
- Integrate and bring up VIPs (DDR_PHY, DDR_Model)
- Develop test stimulus, checkers, scoreboard in SystemVerilog/UVM
- Debug, regression and coverage closure
- Provide debug support to emulation and silicon-bring up teams
- Able to work with teams across the continents
Job Details
Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world.
As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performance, DFD and DFT features around DDR and HBM memory subsystem designs.
Responsibilities
- Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design
- Work closely with 3rd party IP vendors to validate the correctness of integration and custom features.
- Develop testplan and testbench
- Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench
- Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM
- Debug, regression and coverage closure
- Provide debug support to emulation and silicon-bring up teams.
- Able to work with teams across the continents
Key Qualifications
- Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design
- Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx
- Knowledge in the DDR DFI specification and protocol
- Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption
Education and Experience
- Master’s Degree or Bachelor’s Degree with 3-5 years of experience
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