Memory Subsystem Architecture and Performance Modeling
7 Months ago • 3-5 Years
Job Description
Join a well-funded hardware startup in Silicon Valley as a SoC Performance Architect, focused on creating RISC-V based accelerated computing platforms. This role involves defining memory subsystem architecture and microarchitecture, developing performance models in C++ for design space exploration, validating models against specifications, and analyzing performance studies. You will work with architecture and design teams to provide feedback and ensure the quality of models and designs through performance verification tests. The ideal candidate will have strong knowledge of SoC architecture, power/performance trade-offs, and proficiency in C/C++, Python, and simulation techniques.
Good To Have:
- Knowledge of SystemVerilog and waveform debugging tools.
- Experience in different modeling techniques (analytical, event driven, cycle accurate).
- Experience in caches, cache coherency, NOC, LPDDR/DDR/HBM, and IO.
Must Have:
- Define memory subsystem architecture and microarchitecture.
- Develop performance models in C++.
- Validate performance models against specification and RTL.
- Analyze results of performance studies.
- Develop performance verification tests.
- Strong knowledge in SoC architecture and power/performance trade-offs.
- Proficient at SW programming with C/C++, Python.
- Experience in simulators for perf model development and analysis.
- In-depth knowledge of memory subsystem architecture.
- Excellent problem-solving and communication skills.
- Highly self-motivated with strong organization skills.
Join a cutting-edge and well-funded hardware startup in Silicon Valley as a SoC Performance Architect. Our mission is to reimagine silicon and create RISC-V based accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
We are looking for experienced candidates.
Responsibilities
- Define architecture and microarchitecture for memory subsystem components including cache, interconnects and memory.
- Work with architecture and design teams to develop performance models in C++ for design space exploration and provide feedback to architecture and design teams.
- Validate the performance model against the specification and correlate with RTL.
- Plan and analyze results of performance studies analyzing micro-architectural proposals.
- Develop performance verification tests to ensure quality of model and design.
Requirements
- Strong knowledge in SoC architecture and power/performance trade-offs.
- Proficient at SW programming with good understanding of C/C++, Python, and modular object oriented software development.
- Experience in simulators for perf model development and perf analysis. Experience in different modeling techniques from analytical, event driven and cycle accurate.
- In-depth knowledge of memory subsystem architecture, microarchitecture and design including caches, cache coherency, NOC, LPDDR/DDR/HBM, and IO.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Knowledge of SystemVerilog and waveform debugging tools is a plus.
- Ability to work collaboratively in a team and be productive under aggressive schedules.
Education and Experience
- Bachelor’s degree plus 5 years of industry experience.
- Master’s degree plus 3 years of industry experience.
- Ph.D with internship experience.
Set alerts for new jobs by rivos
Set alerts for new jobs in United States
