Senior Member of Technical Staff
Job Summary
Job Description
Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work closely with architects, micro-architects to develop a test plan to be executed for verifying the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments and building test benches in UVM, SV and C. Responsible for developing tests - both directed and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the verification environment. Develop UVM/SV/C based checks for functional correctness, including transaction order, transaction payload construction and transaction responses. Run regressions, debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the fixes in a timely manner. Generate coverage for the design, analyze and close any gaps. Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely with Firmware and Software teams to test the firmware images/ software to be run with PCIe design. Support all verification activities and the SoC through successful tape out. Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the team on PCIe verification activities.
Must have:
- Experience with PCIe protocol on PHY and protocol layers
- Work on verification environments like UVM, System Verilog (SV) and C
- Develop test plans for PCIe verification
- Build test benches in UVM, SV and C
- Develop directed and random tests for PCIe IP/subsystem
- Integrate third-party IPs into verification environment
- Develop UVM/SV/C based checks for functional correctness
- Run regressions and debug failures
- Generate and close coverage gaps
- Collaborate with Firmware and Software teams
Good to have:
- Experience with Cadence tool eplanner
- Developing interface UVC components using UVM
- Creating UVM sequences for complete verification of an ASIC module
- Architecting functional coverage for multiple design modules
- Using Cadence tool eManager for coverage monitoring and closure
- Utilizing Verilog-OVM Methodology
- Scripting Languages (Perl, Python, Tcl/Tk)
- RTL Design, Coding, Simulation, Verification, Place/Route, Logic Validation
4 skills required
Job Details
Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that
support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work
closely with architects, micro-architects to develop a test plan to be executed for verifying
the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments
and building test benches in UVM, SV and C. Responsible for developing tests - both directed
and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the
verification environment. Develop UVM/SV/C based checks for functional correctness, including
transaction order, transaction payload construction and transaction responses. Run regressions,
debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the
fixes in a timely manner. Generate coverage for the design, analyze and close any gaps.
Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely
with Firmware and Software teams to test the firmware images/ software to be run
with PCIe design. Support all verification activities and the SoC through successful tape out.
Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the
team on PCIe verification activities.
Education:
- Master’s or foreign equivalent in Electrical Engineering or related fields
Experience:
- 2 years of experience in job offered or related occupation.
Special Requirements: 2 years of experience must include work with the following technologies:
- Creating verifications plans from the specifications using Cadence tool eplanner.
- Developing interface UVC components using UVM.
- Creating UVM sequences for complete verification of a module of an ASIC.
- Architecting functional coverage for multiple modules of the design and completed the coverage
- Utilizing Verilog-OVM Methodology; Scripting Languages, e.g. Perl or Python or Tcl/Tk.
- RTL Design, Coding, Simulation, Verification, and/or Place/Route; Logic Validation.
monitoring and closure using Cadence tool eManager.
$194,500 - $202,500 a year
Salary
Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054
Applicant Instructions: Email resume to: immigration@rivosinc.com. Must specify job code 90541 in reply. EOE.
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