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RTL Design Lead, Silicon

Karnataka, India (On-site)

RTL Design Lead, Silicon

1 Month ago • 8-12 Years • Research & Development

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Job Description

As an RTL Design Lead at Google, you'll be part of a team developing custom silicon solutions for Google's direct-to-consumer products. You'll lead a team delivering fabric interconnect IP, platforms, and subsystems, driving multi-generation roadmaps for design optimization. Your responsibilities will include defining micro-architecture details, overseeing RTL development, debugging functional and performance simulations, participating in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Must have:

Bachelor's degree in EE, CE, CS or equivalent
8 years of experience with ASIC digital design
4 years of people management experience
Experience with RTL design using Verilog/System Verilog
Experience with ARM-based SoCs, interconnects, ASIC methodology

Good to have:

Master’s degree in EE or CE
Experience with low power estimation, timing closure, synthesis methodologies
Experience leading IP/SoC design team for low power SoCs
Ability to drive multi-generational roadmap for IP/SoC development

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital design in ASIC.
4 years of experience in people management.
Experience with RTL design using Verilog/System Verilog and microarchitecture.
Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

Master’s degree in Electrical Engineering or Computer Engineering.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience leading IP/SoC design team for low power SoCs.
Ability to drive a multi-generational roadmap for IP/SoC development.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

Lead a team that delivers fabric interconnect IP, platforms, and subsystems.
Drive multi-generation roadmap for design optimization.
Define micro-architecture details (e.g., interface protocol, block diagram, data flow, pipelines, etc.).
Oversee RTL development, debug functional, and performance simulations.
Participate in synthesis, timing/power estimation, and Field-Programmable Gate Array/silicon bring-up.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.