Semiconductor Process Engineer, Raxium Display Group
Job Summary
Job Description
Join Google's Raxium display group and contribute to developing custom silicon solutions that power the future of their direct-to-consumer products. As a Semiconductor Process Engineer, you will design and develop a new back-end of line (BEOL) capability, including chemical mechanical polishing (CMP), wafer grinding, and wafer bonding fabrication. You will identify and evaluate quality and implement new equipment or upgrades, review and optimize various wafer fabrication processes for yield improvement, and drive problem resolution for quality excursions in the fab area. This role involves owning the area process control plan and enhancing process stability through best known manufacturing methods and statistical process control (SPC).
Must have:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or related field
- 4 years of experience in Hardware technical environment
- Experience with Semiconductor Engineering and Microelectronics Fabrication
- Experience with Optoelectronics
Good to have:
- Master's degree or PhD in Electrical Engineering, Industrial Engineering, Material Science, Operations Management, Computer Science, Physics, or specialized field
- Experience in Chip-Level Multi-Processing (CMP), wafer grinding, or wafer bonding
Perks:
- Bonus
- Equity
- Benefits
4 skills required
Job Details
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 4 years of experience working in a Hardware technical environment, or 3 years of experience with an advanced degree.
- Experience with Semiconductor Engineering and Microelectronics Fabrication.
- Experience with Optoelectronics.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Industrial Engineering, Material Science, Operations Management, Computer Science, Physics, or a specialized field or equivalent practical experience.
- Experience in the area of Chip-Level Multi-Processing (CMP) or wafer grinding or wafer bonding.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our team combines the best of Google AI, software, and hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.The US base salary range for this full-time position is $142,000-$211,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Design and develop a new back-end of line (BEOL) capability including chemical mechanical polishing (CMP), wafer grinding, and wafer bonding fabrication.
- Identify and evaluate quality and implement new equipment or upgrades.
- Review, propose, optimize, improve, and implement various wafer fabrication processes for yield improvement, defectivity reduction, and manufacturability.
- Own the area process control plan and enhance the process stability through implementation of best known manufacturing methods and statistical process control (SPC).
- Drive the problem resolution process associated with the quality excursion in the fab area encompassing data analytics, methodical problem solving, failure analysis (FA), design of experiments (DOE), and mistake-proof.
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