This role involves designing and integrating custom silicon solutions for Google's products. Responsibilities include owning microarchitecture, implementation, and integration of SoC Chassis and subsystems; performing quality checks (Lint, CDC, RDC, VCLP); driving design methodology, libraries, and debug; and identifying power, performance, and area improvements. The ideal candidate will have experience in ASIC development using Verilog/SystemVerilog, VHDL, or Chisel, along with expertise in ASIC design verification, synthesis, timing/power analysis, and DFT. Experience in SoC integration domains (clocking, debug, fabrics, security, or low power methodologies) is crucial. The position is part of a team pushing the boundaries of hardware innovation to deliver unparalleled performance and efficiency.