SOC Design Verification

3 Years ago • All levels

Job Summary

Job Description

This role is for a full-time SOC verification engineer, focusing on unit to chip level verification. Responsibilities include functional, microarchitecture, and formal verification in areas like DDR memory, Ethernet, PCIe, and Fabric. The engineer will collaborate with architecture and RTL designers, review specifications, develop test plans and environments, write tests in assembly, C/C++, SystemVerilog, or vectors, and implement coverage monitors and checkers. Experience in debugging failures, running simulations, tracking bugs, and assisting with verification flows and automation is required.

Must have:

Work closely with architecture and RTL designers
Reviewing Architecture and Design Specifications
Develop test plans and test environments
Develop tests in assembly, C/C++, SystemVerilog, or vectors
Develop coverage monitors and analyze coverage
Develop checkers in SystemVerilog or C-base transactors
Write assertions and apply formal verification
Implementing test benches
Debugging failures, running simulations, tracking bugs
Handling schedules
In-depth knowledge of digital logic design
Sophisticated knowledge of SystemVerilog
Experienced level knowledge C/C++
Knowledge of verification methodologies and tools

Good to have:

Basic knowledge of formal verification methodology
Excellent knowledge of Python or TCL
Excellent problem solving skills
Excellent communication skills
Excellent organization skills
Highly self-motivated
Ability to work well in a team

4 skills required

4 skills required for this role

Add these skills to join the top 1% applicants for this job

problem-solving

cpp

test-coverage

python

Job Details

Positions are open for full-time SOC verification engineers from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, and formal in particular in the areas of DDR memory, Ethernet, PCIe, and Fabric. We are looking for all levels of talent, from entrance to advanced level of experience.

Responsibilities

Work closely with architecture and RTL designers on verifying the functionality correctness of the design
Reviewing Architecture and Design Specifications
Develop test plans and test environments
Develop tests in assembly, C/C++, SystemVerilog, or vectors according to test plans
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
Develop checkers in SystemVerilog or C-base transactors to verify the design
Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
Debugging failures, running simulations, tracking bugs
Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions

Requirements

In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
Sophisticated knowledge of SystemVerilog.
Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
Basic knowledge of formal verification methodology is a plus.
Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.