CPU Power System Modeling Engineer

6 Days ago • 5 Years + • Research & Development • $132,000 PA - $189,000 PA

Job Summary

Job Description

This role involves developing system-level power models for Google's CPUs, focusing on battery life analysis and energy optimization. Responsibilities include collaborating with SoC and CPU Power teams on power projections, profiling competitor CPUs, workload analysis for battery life, and data mining at the RTL and gate-level for power estimation. The ideal candidate will have experience with low-power dynamic and leakage power estimation, data analytics, flow automation (Python, C, C++, Gemini), and a strong understanding of CPU microarchitecture and power management concepts like DVFS. The position requires driving multiple activities related to CPU architecture, energy modeling, performance analysis, power optimization, and simulation.
Must have:
  • Bachelor's degree in relevant field
  • 5+ years hardware industry experience
  • Low-power estimation & data analytics
  • Flow automation (Python, C, C++)
  • System-level power modeling
  • Power optimization & simulation
Good to have:
  • Master's/PhD in related field
  • CPU microarchitecture knowledge
  • DVFS knowledge
  • CPU benchmarking & performance analysis
Perks:
  • Bonus
  • Equity
  • Benefits

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of experience in the hardware industry or equivalent research.
  • Experience with low-power dynamic and leakage, power estimation, data analytics and profiling.
  • Experience in flow automation (e.g., Python, C, C++, Gemini).

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
  • Knowledge of CPU microarchitecture and system level design.
  • Knowledge of power management concepts, including Dynamic Voltage and Frequency Scaling (DVFS).
  • Knowledge of CPU benchmarking, performance analysis and engaged study.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

  • Own and drive several activities related to CPU architecture and system level energy modeling, engaged performance and power analysis, power optimization, simulation and roll-ups.
  • Develop a system level power model for battery life analysis and energy optimization.
  • Collaborate with the SoC and CPU Power teams on various power projections and requirements for our CPU, including silicon power capture and profiling of competitor CPUs for benchmarks and other daily workloads.
  • Perform workload analysis for battery life and tests definition for power analysis and optimization.
  • Perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation.

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