Senior Staff RTL Design Engineer

4 Months ago • 5-12 Years • Research & Development

Job Summary

Job Description

Marvell seeks a Senior Staff RTL Design Engineer with 5-12 years of experience in digital design microarchitecture development and RTL coding in Verilog or SV. Must have experience in logic synthesis, constraint development, backend flow, and static timing analysis.
Must have:
  • Digital Design
  • RTL Design
  • Verilog/SV
  • Logic Synthesis
Good to have:
  • Ethernet Protocols
  • Encryption Algorithms
  • PTP Protocol
  • GIT Version Control
Perks:
  • Competitive Compensation
  • Great Benefits

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, develop switching solutions and work with the world’s leading data center and enterprise companies to bring next generation networking to reality.

What You Can Expect

  • Own a significant section of our Switch design
  • Take it from Micro-architecture to Tape out.
  • Work closely with Architects
  • Be responsible for coding of the micro-architected design
  • Integrate 3rd party IP
  • Work with DFT team to integrate test features
  • Work with DV team to ensure feature coverage and debugging
  • support physical design team for timing analysis/timing closure.

What We're Looking For

  • 5 – 12 years’ of relevant industry experience.
  • Experience with digital design microarchitecture development is a must.
  • Design/RTL experience in Verilog or SV is a must.
  • Experience with logic synthesis, synthesis constraint development and backend flow and static timing analysis.
  • Knowledge of scripting languages, such as PERL, Python
  • Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols) preferred.
  • L2 / L3 / L4 Ethernet protocol knowledge
  • Encryption / Authentication algorithms.
  • Precision Time Protocol (PTP, IEEE-1588)
  • Knowledge of GIT version control system
  • Good learning , problem solving interpersonal and communication skills.
  • Ability to be a part of a team, working in cooperation.
  • Self-motivated team player able to thrive in a fast-paced engineering environment

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

#LI-CP1

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