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Summer Intern, Design Verification

Arizona, United States (On-site)

Summer Intern, Design Verification

2 Months ago • All levels • Research & Development

About the job

2 skills required for this role

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foundation

innovation

Job Description

Cirrus Logic seeks a Summer Intern to assist with pre-silicon verification of mixed-signal products. Must have a strong background in Verilog/SystemVerilog and be pursuing an MSEE/MSCE with a GPA of 3.6 or above. This internship is on-site in Chandler, Arizona.

Must have:

BSEE/BSCE
MSEE/MSCE
Verilog / SystemVerilog
Verification planning

Good to have:

UVM
Assertions
Functional Coverage
Constrained-Random Verification

Perks:

Award-winning culture
Meaningful community engagement

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For nearly four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

Cirrus Logic's Design Verification Engineering team is looking for an intern who will work as a part of the design verification team to perform pre-silicon verification on mixed-signal products using SystemVerilog, UVM, and other verification techniques such as assertions, functional coverage, and constrained-random verification. Our intern will work closely with digital designers, firmware developers, and systems engineers to support pre-silicon verification.

RESPONSIBILITIES:

Assist with verification planning.
Support with testbench development
Maintenance with failure analysis and resolution
Help with coverage analysis and population
Work on digital/mixed-signal modeling, directed/constraint-random test generation, and flow development

REQUIRED KNOWLEDGE, SKILLS AND EXPERIENCE:

Must have a BSEE/BSCE and be pursuing an MSEE/MSCE
Strong background with Verilog / SystemVerilog

This internship is on-site. This opportunity is available for the summer semester only. It is available only to students currently enrolled in a MS or PhD program in Electrical Engineering maintaining a GPA of 3.6 or above, and who will be returning to school for at least one semester following completion of his/her internship. Candidate must be available for full-time employment during the internship.

Diversity drives innovation at Cirrus Logic. Different approaches, ideas and points of view are both valued and respected, and employees are rewarded for their skills, experience and performance. Additionally, Cirrus Logic is an Equal Opportunity/Affirmative Action Employer, and we do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.

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