TPU Silicon System Integration and Validation Engineer
Job Summary
Job Description
- Bachelor's/Master's in relevant field
- 2+ years experience in silicon IC development
- HW/SW integration and validation experience
- RTL development or evaluation experience
- Experience in computer architecture, compilers, computer arithmetic, ASIC design
- Master's/PhD in relevant field (computer architecture emphasis)
- FPGA/emulation/silicon HW experience
- RTL simulation/emulation/FPGA experience
- Verilog/RTL coding, waveform debug, chip design flows
- SW development (C/C++), scripting (Python), embedded firmware
5 skills required
Job Details
Minimum qualifications:
- Bachelor's or master's degree in Electrical Engineering, Computer Engineering or Computer Science or related field.
- 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience in HW/SW integration and validation.
- Experience with RTL development or evaluation.
- Experience in the following areas: computer architecture, compilers, computer arithmetic, ASIC design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 3 years of experience working on FPGA or emulation or silicon HW environments.
- 2 years of Experience working with RTL Simulation OR Emulation/FPGA technologies.
- Experience writing or debugging verilog / RTL code for ASIC or FPGA designs, waveform debug skills and knowledge of chip design flows.
- Experience in SW development in C or C++, scripting in python or similar. Experience in embedded Firmware development.
About the job
In this role you will be working on ASIC development, validation, software, tools, and methodologies and have the ability to push the boundaries of chip-development and hardware/software integration and validation.
You will contribute to cross-functional work streams focused on Hardware/Software(HW/SW) integration and validation to demonstrate HW, SW, and system functionality and performance. Help the chip team accomplish silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments. Serve as a bridge between specification, design, and verification teams as well as compiler and performance teams with technical and breadth across the Machine Learning compute IP.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Review chip specs, plan HW/SW integration, coordinate delivery, and benchmark performance with system partners. Enable bringup of the Machine Leaning (ML) Compute features through compiler stack and ML workloads. Integrate and validate hardware and software designs in pre-silicon.
- Craft HW-SW co-simulation using RTL, emulation, FPGA, and architectural models for performance correlation.
- Drive debug discussions with Design/DV/SW/Arch teams and help root-cause functional failures and performance issues through the product development cycle. Improve validation coverage and sign-off processes for quality tapeout and production deployment.
- Plan and design validation tests and microbenchmarks to validate IP functionality and performance. Develop detailed test plans, based on design specifications coordinated with a cross-functional team (e.g. design, DV, firmware, compiler, architecture).
- Analyze ML workload performance pre/post-silicon, contributing to compiler and next-gen chip.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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