ASIC RTL Design Engineer
Job Summary
Job Description
- 3+ years RTL coding (Verilog/SystemVerilog)
- Experience with EDA tools
- ASIC/SoC subsystem design
- RTL design and implementation
- SystemVerilog RTL development
- Master's/PhD in relevant field
- 5+ years ASIC design experience
- Interconnect and network subsystem experience
- Bonus
- Equity
- Benefits
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with Register-Transfer Level (RTL) coding using Verilog/SystemVerilog.
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 5 years of experience in Application-specific integrated circuit (ASIC) design.
- Experience working on interconnects and network subsystems.
About the job
As a Design Engineer, you will play an important role in designing ASIC/SoC hardware for Artificial Intelligence (AI) and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration.
In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on chip-to-chip interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Work separately and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
- Work with design validation (DV) teams to create testplans for, verify, and debug design RTL.
- Work with architecture and power teams to evaluate features and their impact.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
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