Backend Engineer, Full Chip Layout

3 Weeks ago • 4-6 Years • Research & Development

Job Summary

Job Description

NVIDIA seeks experienced Backend Engineers specializing in full-chip layout physical design for high-speed communication devices. Responsibilities include full-chip layout implementation and analysis, resolving complex layout and congestion issues, performing DRC, LVS, and ANT verification, and contributing to process improvements. The ideal candidate will have 4-6 years of experience in BE/LO engineering, proficiency in physical design flows and EDA tools (Synopsys, Cadence), and excellent communication skills. This role involves working on challenging designs with high cell counts and high-speed blocks, contributing significantly to groundbreaking chip development within a highly professional and collaborative environment.
Must have:
  • 4-6 years BE/LO experience
  • Full chip layout implementation
  • DRC, LVS, ANT expertise
  • Proficiency in EDA tools
  • Strong communication skills
Good to have:
  • Knowledge of PNR, STA
  • Experience with high cell count designs
  • Problem-solving skills

Job Details

NVIDIA is looking for best-in-class full chip layout Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

  • Full Chip Layout implementation and analysis of partition groups / top-level according to specifications, under challenging constraints, targeting for the area, route and integration.

  • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex layout and congestion problems.

  • Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT for partition groups and full chip level.

  • Taking part inflows development.

What we need to see:

  • B.SC. in Electrical Engineering/Computer Engineering.

  • 4-6 years of experience as BE/LO engineer.

  • Ability to quickly adapt to new technology and go deep into new areas

  • Strong communication skills

  • Great teammate.

  • Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

  • Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

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About The Company

Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.


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