Custom Design Static Timing Analysis Engineer, Silicon

1 Month ago • 5-10 Years • Research & Development

Job Summary

Job Description

This role involves performing Static Timing Analysis (STA) on mixed-signal designs to ensure all timing requirements are met. Responsibilities include analyzing digital path timing, developing and maintaining STA constraints and scripts, creating accurate timing constraints for the entire chip (including digital and mixed-signal portions), ensuring constraint consistency with design specifications, and developing methodologies for IP collateral generation and QA checks. The ideal candidate will have 5+ years of experience in STA with mixed-signal designs, proficiency in tools like HSPICE, Nanotime, Liberate, Silicon Smart, or Virtuoso, and scripting skills (Perl, Python, TCL). The position contributes to the development of custom silicon solutions powering Google's direct-to-consumer products.
Must have:
  • 5+ years STA experience (mixed-signal)
  • Experience with HSPICE, Nanotime etc.
  • Perl, Python, TCL scripting
  • Timing flow methodology development
  • STA constraint creation & maintenance
Good to have:
  • Master's/PhD in relevant field
  • 10+ years STA experience (Analog/mixed-signal)
  • IP collateral generation/QA experience
  • Cadence/Synopsys tools experience

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, a relevant technical field, or equivalent practical experience.
  • 5 years of experience in static timing analysis with mixed- signal designs.
  • Experience in timing flow methodology and development.
  • Experience in HSPICE, Nanotime, Liberate, Silicon Smart, or Virtuoso.
  • Experience in coding using Perl, Python, TCL scripting languages.

Preferred qualifications:

  • Master's degree or PhD in Computer Science, Electrical Engineering, or a related field.
  • 10 years of experience in STA with experience on Analog/mixed signal designs.
  • Experience with IP collateral generation/QA.
  • Experience in Cadence/Synopsys tools.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Perform (Static Timing Analysis) STA on mixed-signal designs to verify that all timing requirements are met. This involves analyzing the timing of digital paths within the chip.
  • Develop and maintain STA constraints and scripts.
  • Create and maintain accurate timing constraints for the entire chip, including both digital and mixed-signal portions.
  • Ensure that constraints are consistent with the design specifications.
  • Develop flow and methodology for IP collateral generation and Quality Assurance (QA) checks.

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