EDA Workflow Optimization Engineer

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering teams worldwide. You will understand workflows covering the full chip design process from inception through study, architecture, design, verification, emulation, layout, packaging, power-on and production. You will then guide teams to improve, and sometimes re-invent those flows. You will enable our engineers to have the best tools on the planet to make the most innovative chips in the world. You will perform investigations to understand flaws and opportunities, create metrics to continuously measure performance of our flows and services, and other infrastructure. You will work with your team of EDA and software experts to build new infrastructure in an agile, production software environment. You will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of chips!

What you’ll be doing:

• Work in a diverse team performing fast paced investigations to empower our engineers to develop at the speed of light.

• Participate in the full life cycle of tool development, test, and deployment.

• Work closely with other team members and chip engineers to understand and improve their workflows and needs.

• Build metrics that are reliable and easy to use by hundreds of engineers around the world.

• Architect security mechanisms to protect intellectual property.

• Directly contribute to the overall quality of and improve time to market for of our next generation chips.

What we need to see:

• MS (preferred) or BS in Computer Science with 2+ years of relevant experience.

• Strong experience investigating and debugging complex problems in Unix environment.

• Experience with all stages in the ASIC design flow

• Hands-on experience with EDA tools

• Experienced level in Unix Systems Programming

• Authoritative level usage of Unix and Unix utilities

• Excellent planning and communication skills

• Experience in applying data analysis principles and influencing data-driven decisions.

• Flexibility/adaptability working in a dynamic environment with changing requirements.

Ways to stand out from the crowd:

• Experience with VLSI, CAD/EDA or digital design, IBM Spectrum LSF, strong programming and debugging skills with C/C++ and Python on Unix, deep understanding of distributed system principles.

• Hands-on experience running GPU-based workloads in a batch computing environment, experience with chip design workflows, RTL verification flow.

• Experience with export control compliance, background in IT Security,

• Hands on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers

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