NVIDIA seeks a Layout Design Engineer to execute IC layouts for cutting-edge, high-performance, high-speed CMOS integrated circuits in advanced nodes (3nm, 5nm, 7nm, and below).  Responsibilities include delivering layouts for digital and analog IPs, implementing best layout practices, following company procedures, and collaborating within a distributed team.  The ideal candidate possesses 2+ years of high-performance analog layout experience in advanced CMOS processes, expertise in Cadence EDA tools, and knowledge of high-speed IO and analog layout guidelines.  Experience with analog blocks (current mirrors, sense amps, bandgaps) and sub-micron design is preferred.

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<div data-automation-id="jobPostingDescription" class="css-4r17ng">NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!We are looking for an Layout Design Engineer&nbsp;– someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs.&nbsp;What you'll be doing:<ul><li>Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices.</li><li>Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.</li><li>IP layout will&nbsp;comprise&nbsp;of significant digital components and some analog components.</li><li>Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts</li><li>Follow company procedures and practices for IC layout activities.</li></ul>&nbsp;What we need to see:<ul><li>2+ years of experience in high performance analog layout in advanced CMOS process.</li><li>BE/M-Tech in Electrical &amp; Electronics or equivalent experience.</li><li>Thorough knowledge of industry standard EDA tools for Cadence.</li><li>Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.</li><li>Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)</li><li>Experience with floor planning, block level routing and macro level assembly.</li><li>Knowledge of high-performance analog layout techniques such as common centroid layout, matching,&nbsp;symmetrical layout, signal shielding,&nbsp;use of dummy devices, thermal aware layout with consideration for electro migration and&nbsp;other analog specific guidelines.</li><li>Demonstrated experience with analog layout for silicon chips in mass production.</li><li>Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.</li><li>Experience working in distributed design team is a plus.</li><li>Requires self-starter with the ability to define and adhere to a schedule.</li></ul>&nbsp;We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.#LI-Hybrid</div>

Layout Design Engineer