Principal Memory Controller Architect

As the Principal Memory Controller Architect in the silicon engineering organization, you will be part of the team that defines the overall Memory Controller Architecture. You will collaborate closely with various teams, including product and platform architecture, peer System on Chip (SoC) architects, IP architects, Performance/Modeling architects, Software (OS and Hypervisor) and Firmware architects, Design, Validation, and Execution teams, etc., to ensure our SOCs and IPs enable high performance, efficiency, reliability, and industry-leading systems. This team engages in multiple projects within Microsoft, developing custom silicon for a variety of systems. We are committed to delivering advanced, custom SoC designs capable of performing complex and high-performance functions in the most efficient way possible.

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CCDO team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Memory Controller Architect to join the team.

Required/Minimum Qualifications

• 11+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• 10 + years of experience in computer architecture, SoC and system Hardware and Software architecture, and the associated tradeoffs
• 10 + years of experience in cache and memory controller architecture, micro architecture, design and verification
• 10 + years of experience in developing a DDR memory controller and taking it from pre-silicon definition to mass production

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

• 18+ years of technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 15+ years of technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 10+ years of technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years of technical engineering experience.
• Excellent communication, collaboration and teamwork skills and the ability to contribute to diverse and inclusive teams

Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $161,600 - $286,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $209,600 - $314,400 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 17, 2024

• Architect and develop memory controllers for a variety of memory technologies.
• Review and analyze memory technology roadmaps, including DDR, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM/MRDIMM, and emerging memory technologies.
• Collaborate with memory controller micro-architects, as well as verification and validation teams, to productize new features.
• Work with vendors to evaluate intellectual property (IP) and make recommendations for integration.
• Collaborate with the Performance Modeling team to develop cycle-approximate models for memory controllers and analyze System on Chip (SOC) /platform performance, particularly with Azure workload results.
• Partner with Strategic Planning, Architecture, and internal customers to understand workload and use case requirements, focusing on full-stack optimization opportunities within the memory hierarchy.
• Foster cross-team collaboration to develop the best solutions with a One Microsoft mindset.
• Challenge the status quo with a growth mindset to drive innovation and enable world-class SOC products across Microsoft.