SoC and IP Design Engineer
Job Summary
Job Description
- 5+ years experience in digital design
- RTL design (Verilog/SystemVerilog)
- Synthesis, timing/power closure
- Design verification & debug
- Lint/CDC/FV/UPF checks
- Python/Perl coding
- High-performance/low-power design
- Assertion-based formal verification
- SoC architecture knowledge
- PCIe, UCIe, DDR, AXI, or ARM processor experience
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
- Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques.
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
- Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
- Experience in coding languages like Python or Perl.
- Knowledge of high performance and low power design techniques.
- Knowledge of assertion-based formal verification.
- Knowledge of System-on-a-Chip (SoC) architecture.
- Knowledge of PCIe, UCIe, DDR, AXI or ARM processors.
About the job
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
- Participate in test plan and coverage analysis of the block and SoC level verification.
- Communicate and work with multi-disciplined and multi-site teams.
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