SoC and IP Design Engineer
Job Summary
Job Description
- 3+ years digital logic design experience
- RTL design (Verilog/SystemVerilog)
- Logic synthesis & verification
- SoC/block level design documentation
- ASIC bring-up & test plan creation
- Design sign-off tools (Lint, CDC)
- Scripting (Python/Perl)
- PCIe, UCIe, DDR, AXI, ARM knowledge
- Formal verification
- High-performance/low-power design
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
- Experience in logic design and debug with Design Verification (DV).
Preferred qualifications:
- Experience with design sign off and quality tools (e.g., Lint, Cyber Defense Center (CDC), etc.).
- Experience with a scripting language like Python or Perl.
- Knowledge in one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
- Knowledge of SOC architecture and assertion-based formal verification.
- Knowledge of high performance and low power design techniques.
About the job
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
- Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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