Staff Engineer, SOC Static Timing Analysis (STA)

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What You’ll Do

The Advanced Controller Development (ACD) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash.  ACD’s vision is to solve critical challenges in Cloud & Data center by developing the new technology for storage (SSD) controller. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

We are seeking an SOC Static Timing Analysis (STA) Engineer will focus on enhancement of storage (SSD) capability by developing the prototype controller and optimize it for mass production. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing.

Location: Onsite at our Folsom office/headquarters 5 days a week

Reports to: Senior Director

• Performs all aspects of the physical implementation flow for a highly complex SoC using the state of the art process technology.
• Collaborate with design team to understand timing constraints to meet timing requirements.
• Perform complex SoC level synthesis with the constraints.
• Perform STA (Static Timing Analysis) to identify the critical timing path.
• Work with design, verification, and place and route team to address the design challenge in the timing sign-off.
• Work closely with third party design services to deliver the high quality of the design that meets PPA goals.
• Complete other responsibilities as assigned.

 What You Bring

• Bachelors in Computer/Electrical Engineering or related degree with 5+ years of experience or Masters in Electrical Engineering, Business, or comparable engineering degree with 3+ Years of Industry Experience Preferred.
• 5+ years working experiences in storage industry, data center technologies, or cloud infrastructures
• Experience in synthesis.
• Experience with large design STA and timing closure.
• Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
• Experience in ECO technique and implementation.
• Deep understanding of flash memory controller architecture, and related IP design, verification, SOC implementation process and tools.
• Working knowledge of storage technologies (NAND flash, SSD, etc.), especially for datacenter scale product (requirement, usage, etc.)
• Strong understanding of server memory and storage hierarchies, the existing and emerging technologies that could be utilized at each level, and the potential performance trade-offs and optimizations involved.
• Thorough knowledge of general computer architecture: computer/server systems, processors, storage, I/O, network, data centers, and typical applications.
• Understanding of the emerging technologies (CXL, Computation in memory and storage, Ethernet-attached SSD etc.) in server memory and storage systems
• Experience with evaluating the emerging challenges and opportunities in server memory and storage systems in 2015 and beyond.
• Experience with performance modeling of embedded systems is beneficial.
• Ability to meet aggressive project deadlines in a team environment
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

 #LI-MD1

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