Analog IC Design Intern - Masters

6 Months ago • Upto 4 Years • Research & Development

Job Summary

Job Description

Marvell seeks a Masters-level Analog IC Design Intern to design, lay out, and verify FET and BiCMOS circuits for high-speed broadband ICs. Must have expertise in Opamps, VGAs, High-Speed Drivers, TIAs, Mixers, and VCOs. Experience with Cadence design software is preferred.
Must have:
  • Analog IC Design
  • Circuit Design
  • Cadence Virtuoso
  • Device Physics
Good to have:
  • SiGe Bipolar
  • CMOS
  • Electro-magnetic Analysis
  • Planar Inductors
Perks:
  • Competitive Compensation
  • Great Benefits

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Broadband Access group designs physical layer ICs for high-speed fiber optic data communication, such as Transimpedance Amplifiers (TIAs), and drivers for Silicon Photonic (SiPho), discrete Electro-absorption Modulators (EAMs) and Mach-Zehnder Interferometer Modulators (MZMs). This group is the market leader in delivering TIAs and Drivers that support 10Gbps to 800Gbps systems. We address the bandwidth, capacity and power issues faced by cloud computing and mega data center networks. Our world class group leverages our core competencies in advanced circuit design to solve the world’s ever-increasing desire to transmit more data for less power with fewer errors. We are continually first to market in Data Center, Metro and Long-Haul applications.
As a member of the design group, the candidate will be responsible for design, layout and verification of FET and BiCMOS circuits for high-speed broadband ICs that serve these applications.

What You Can Expect

  • Understand the requirements of the product and how your block fits into it.
  • Capture schematics in Cadence Virtuoso
  • Investigate new architectures to come up with the best choice for the requirements.
  • Perform layout of an integrated circuit block.
  • Create an extracted model of the design.
  • Run simulations to verify the performance of the design.
  • Document the design and hold a design review with the design team.

What We're Looking For

Looking to fill a 4 to 8 month position with a flexible start date.

Minimum Requirements:

  • Candidate MUST be currently pursuing a MSc or PhD degree in EE or related technical field(s)
  • Detailed understanding of various different circuit blocks such as:
  • Opamps, VGAs, High Speed Drivers, TIAs, Mixers, VCOs.
  • Ability to analyze feedback networks.
  • Familiarity with layout.
  • Understanding of device physics.
  • Strong communication, presentation, and documentation skills

Preferred Requirements:

  • Knowledge of Cadence design software.
  • Knowledge of SiGe Bipolar as well as CMOS is a plus.
  • Ability to perform electro-magnetic analysis and simulation of planar inductors, trasmission lines and t-coils.
  • 0-4 years of previous industry experience

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

#LI-SC1

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