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DFT Lead, Google Cloud

Haifa District, Israel (On-site)

DFT Lead, Google Cloud

1 Month ago • 8-12 Years • Research & Development

About the job

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Job Description

As the Design For Testing (DFT) Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tape-out. You will lead and execute activities in the design, implementation, and verification of DFT solutions for ASICs. You will also develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG). You will work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed. You will also manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team. You will lead DFT execution of a silicon project including planning, execution, tracking, quality, and signoff.

Must have:

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in DFT structural/functional at Pre and Post Silicon
4 years of people management experience developing employees
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow
Experience in leading DFT activities throughout an ASIC development flow

Good to have:

Master's degree in Electrical Engineering or a related field
Experience in JTAG and iJTAG protocols and architectures
Experience in post-silicon test or product engineering
Experience in SoC cycles, silicon bring-up, and silicon debug activities
Knowledge of fault modeling techniques

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in DFT structural/functional at Pre and Post Silicon.
4 years of people management experience developing employees.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Lead and execute activities in the design, implementation, and verification of DFT solutions for ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project including planning, execution, tracking, quality, and signoff.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.