Intel is seeking a Performance/Power Optimization Product Engineer Graduate Intern to analyze and enhance the 14A Technology node offering from a customer's perspective. This role focuses on improving design collateral offerings such as PDK, PNR, and PPA to increase ease-of-use for end customers. You will collaborate with Intel experts to refine and optimize our technology offerings, contributing to the advancement of semiconductor design. 

In this role, your responsibilities will include:   

• Analyze customer feedback and requirements to identify areas for improvement in the 14A Technology node offering. 

• Collaborate with cross-functional teams to enhance design collateral offerings, including PDK, PNR, and PPA. 

• Develop strategies to optimize power consumption, performance metrics, and area efficiency in semiconductor designs. 

• Conduct research and apply advanced techniques to improve the usability and effectiveness of design tools. 

• Present findings and recommendations to stakeholders to drive continuous improvement in product offerings. 

• Run and analyze Ring Oscillators (RO) or Place and Route (PNR) studies to establish technology node value. 

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.  

Minimum Qualifications:   

• Pursuing a Master's Degree in Electrical Engineering, Electronics and Communication Engineering, or a related STEM field. 

• Analyzing and optimizing designs to improve power consumption, performance metrics, and area efficiency using synthesis or PNR tools 

• Creating and optimizing custom integrated circuits, particularly in analog, mixed-signal, and RF domains. 

Preferred Qualifications: 

• Expertise in SRAM design or standard cell design. 

• IR drop analysis, STA, leakage recovery, or other signoff domains. 

• Experience running ring oscillators or other spice simulations. 

• Experience running place and route (P&R) tools. 

Join our team of innovators and contribute to shaping the future of Intel's technology offerings!