ASIC Design Engineer, Platform IP, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power design techniques.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.
• Experience with a scripting language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 3 years of experience with Intellectual Property (IP) design for clocking, interconnects or peripherals.
• Experience with methodologies for low power estimation, timing closure, or synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).