Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. The Semi-custom and Central IP Silicon (SCIPS) team is seeking passionate, driven, and intellectually curious Design Verification Engineer who can work with cross-discipline teams to develop the environment and test cases to verify IP designs. The candidate should be passionate about developing systematic and efficient methods to detect hardware/software vulnerabilities.

Join our team and help create critical IPs for various Microsoft teams. You'll be developing custom silicon for a diverse array of systems, from cutting-edge consumer products like Xbox to Azure cloud servers, clients, and IoT SOCs

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. 

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Required Qualifications 

• 5+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience or internship experience.

• 3+ years of experience in developing test plans, creating simulation environments, developing tests, and debugging for multiple IPs, SoCs or systems.
• Proficient in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl. 

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

• 8+ years technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• In depth knowledge of verification principles, testbenches, stimulus generation. 

• Substantial background in creating UVM environments, developing tests, and debugging designs. 

• Solid understanding of chip and/or computer architecture. 

• Experience writing tests in C and C++. 

• Scripting language such as Python, Ruby, or Perl.

• Experience with secure hardware design for embedded systems. 

• Experience with hardware emulation or FPGAs. 

• Experience in RTL design for FPGA or emulation. 

• Experience in Assembly, start up code and linker scripts. 

• Experience in developing makefiles for software development. 

Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $98,300 - $193,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $127,200 - $208,800 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 11, 2025

• Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Develop tests using UVM or C/C++.
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Embody our and