Floating Point Datapath Microarchitect

5 Days ago • 8-11 Years

About the job

Summary_{By Outscal}

MIPS seeks a Floating Point Datapath Microarchitect with expertise in high-performance FPU design. Must have knowledge of pipeline stages, IEEE compliant FP design, experience with FP16/32/64, bfloat16 modes, System Verilog, and verification tools.

We are seeking an experienced Floating Point Datapath CPU Micro architect. Responsible for defining, leading and owning RTL development of a high-performance Floating-Point Unit. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area.

You will:

Drive the micro-architecture and design of a Floating-Point scalar and vector Arithmetic and Logical operations.
Explore high-performance strategies working with the Floating-Point Unit (FPU) modeling team
Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications
Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Perform Functional verification support and assist in the design verification strategy
Assist with the verification of RTL design performance goals
Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Ideally, you’ll have:

Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance FPU is required.
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
High-performance Floating-Point Adder, Multiply, Divide, Sqrt
IEEE compliant Floating-Point design
Experience with supporting FP16, FP32, FP64, bfloat16 modes
Experience with designing narrowing and widening datapaths
Integer and Floating-point execution
Knowledge of System Verilog, Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Experience with datapath formal verification tools
Knowledge of logic design principles along with timing and power implications
Master’s with 8-11 years of experience, PhD + 5-7 years of work experience

Here’s what you can expect from us:

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.