Hardware Architect, GPU, ML IP
Job Summary
Job Description
- 5+ years ASIC hardware architecture and silicon design experience
- Experience architecting low-power multimedia hardware IP
- Collaboration with cross-functional teams
- Define and deliver hardware architecture meeting power, performance, and image quality goals
- Master's or PhD in EE/CE/CS
- Experience with Camera ISP, video codecs, display, graphics, and machine learning networks
- Experience in ultra-low power SoC applications
- Knowledge of interconnect/fabric, security, multi-level caching architectures
- Bonus
- Equity
- Benefits
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of work experience in ASIC hardware architecture and silicon design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience architecting and designing low power multimedia hardware IP for SoCs in the following areas: Camera ISP, video codecs, display, graphics and machine learning networks.
- Experience collaborating cross-functionally with product management, SoC architecture, IP design and verification, camera, video, machine learning algorithm and software development teams.
- Experience in architecting hardware and workflows for ultra low power SoC applications.
- Experience in micro architecture, power and performance optimization.
- Knowledge of interconnect/fabric, security, multi-level caching architectures.
About the job
In this role, you will contribute your ASIC architecture in hardware solutions for Camera ISP, Video, TPU, GPU and Display IP. You will collaborate with Camera, Video, Display, Machine Learning Algorithm teams to architect power, performance, area and IQ engaged hardware IP solutions and develop the architecture specifications used by the hardware IP design teams to implement the solutions within the SoC. You will work cross-functionally with many teams across Google to define engaged and differentiating user experiences on Google hardware devices and drive these user experiences into Google silicon.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Define and deliver the hardware Graphics/Machine Learning IP architecture that meet engaged power, performance, area and image quality goals, which will require owning the targets through to tape-out and product launch.
- Collaborate with Graphics, Camera, Video, Display and Machine Learning software, system and algorithm engineers to co-develop and specify competitive hardware IP architectures for integration into SoCs.
- Collaborate with GPU, TPU, camera ISP, video and display hardware IP design teams across global sites to drive the hardware IP architecture specifications into design implementation for SoCs.
- Collaborate with SoC and System/Experience architects on meeting power, performance and area requirements at the SoC level for multimedia use cases and experiences.
- Perform detailed data analysis and tradeoff evaluations to improve multimedia architecture solutions.
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