OnSemi is seeking a Principal Physical Design Engineer with 8+ years of experience in ASIC/Mixed signal chip developments. You'll lead P&R, power planning, floor planning, clock tree building, and congestion analysis for complex multi power domain designs. Strong understanding of RTL design, ASIC synthesis, timing analysis, CDC, P&R, UPF, Verilog, TCL, Perl/Python, and XML programming languages are required.
Must have:
ASIC/Mixed signal
RTL design, ASIC
Timing analysis, CDC
P&R, UPF, Verilog
Good to have:
TCL, Perl/Python
Power planning, Floor
Clock tree building
Congestion analysis
Perks:
OnSemi benefits
Great place to work
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About the job
Job Description OnSemi is seeking a Principal Physical Design Engg, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following:
P&R Lead with hands on experience in P&R, power planning, floor planning, clock tree building, congestion analysis for complex multi power domain designs
Strong in problem solving with deep understanding of technical issues.
Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.
The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status
Good understanding of IR & power analysis and hands on experience in using related tools/flows
Solid understanding of Verilog, TCL and Perl/Python programming languages
Responsibilities
BS in Electrical Engineering or related + 8 years of experience, or MS + 7 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
Solid understanding of RTL design, ASIC synthesis, timing analysis and CDC, P&R, UPF
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Solid track record of releasing complex ICs to market
Ability to clearly articulate issues, challenges, and concerns to all levels of management
Must have good written and verbal cross-functional communication skills
Qualifications
BS in Electrical Engineering or related + 8 years of experience, or MS + 7 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
Solid understanding of RTL design, ASIC synthesis, timing analysis and CDC, P&R, UPF
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Solid track record of releasing complex ICs to market
Ability to clearly articulate issues, challenges, and concerns to all levels of management
Must have good written and verbal cross-functional communication skills
About Us onsemi(Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits About The Team We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.
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