OnSemi is seeking a Principal Physical Design Engineer with 8+ years of experience in ASIC/Mixed signal chip developments. You'll lead P&R, power planning, floor planning, clock tree building, and congestion analysis for complex multi power domain designs. Strong understanding of RTL design, ASIC synthesis, timing analysis, CDC, P&R, UPF, Verilog, TCL, Perl/Python, and XML programming languages are required.