Senior Tensor Processing Unit Architect, Silicon
Job Summary
Job Description
- 5+ years TPU or parallel processor architecture experience
- Experience in silicon design
- Expertise in micro-architecture, power and performance optimization
- Cross-functional collaboration experience
- Machine learning algorithm and workload analysis expertise
- Master's or PhD in relevant field
- Experience with TPU hardware IP design for SoCs
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience working with TPU or parallel processor architecture (such as VPU/DSP) and silicon design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- Experience in micro-architecture, power and performance optimization.
- Experience collaborating cross-functionally with SoC architecture, IP design and verification, algorithm and software development teams.
- Experience in machine learning algorithm, workloads analysis, performance/power evaluation, and architecture optimizations.
- Experience with architecting and designing TPU hardware IP (or machine learning accelerator) for SoCs.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a member of the CoreIP Hardware Architecture team, you will contribute your architecture expertise in providing hardware solutions for TPU architecture. You will collaborate with algorithm, power and performance teams in Performance, Power, Area (PPA) optimizations and develop the architecture specifications used by the hardware IP design teams to implement the solutions within the Security Operations Center (SoC).
In this role, you will work cross-functionally with many teams across Google to define key differentiating user experiences on Google hardware devices and drive these user experiences into Google silicon.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work on TPU (Tensor Processing Unit) architecture for the next-generation Tensor SOC to boost Performance, Power and Area based on machine learning workload analysis.
- Define and deliver the TPU hardware IP architecture specifications that meet power, performance, area goals, owning the goals through to tape-out and product launch.
- Perform detailed data analysis and tradeoff evaluations to improve our TPU architecture solutions.
- Propose architectural features/requirements for TPU to integrate TPU with Tensor SOC to improve overall performance.
- Collaborate with implementation teams to drive the TPU hardware IP architecture specifications into design implementation for SoCs.
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