Digital Design (Senior to Senior Staff level)

Your Team, Your Impact

Marvell is a leading provider of innovative storage technologies, including ultra-fast read channels, high-performance processors, leading-edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems.

Marvell Vietnam is one of Marvell Research and Development (R&D) centers. We are seeking talented engineers to join our ASIC Development team and work with the most advanced technologies in IC design.

What You Can Expect

• Work with IP/SoC architecture to study design feasibilities meeting PPA requirements.
• Create Micro-architecture specification (MAS), perform RTL coding based on MAS using best RTL coding practices, and integrate the RTL into the IP/SoC.
• Perform RTL code review, apply tools to formally check/fix RTL against various design rules.
• Work with the verification team to define test-plan, debug/fix failures, analyze coverage.
• Define verification strategy and do verification to make sure verification closure.
• Cooperate with Synthesis, DFT, STA, PnR teams to solve issues related to in-charged IP.
• Support Emulation, FPGA prototype, functional ATE, and silicon validation teams

What We're Looking For

• Degree in Computer Science, Electrical Engineering, or related fields and 6+ years of related professional experience. Less experienced candidate with 8+ educational GPA are welcome. PhD candidates with limited work experience are encouraged to apply
• Proven track record of digital IP design from concept to successful ASIC/SoC project TOs.
• Familiar with digital IC design methodologies, understand all stages of ASIC design flows, and experienced EDA tools.
• Hands-on behavioral and RTL coding experience, Verilog/SV preferred.
• Hands-on verification different abstract levels including block, IP and SoC
• Strong knowledge of verification methodology, logic synthesis and timing analysis.
• Good at documentation and communication skills using English.
• Experiences in UVM verification methodology is a plus
• Experiences in PCIe/DDR/SRAM/NVMe/DMA/Security/RISC-V IP is a big plus.
• Experiences in USB/SAS/SATA IP, ARM-based SoC, Emulation, FPGA is a plus