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Senior Product Engineer

California, United States (On-site)

Senior Product Engineer

4 Hours ago • 3-8 Years • Quality Assurance • $117,200 PA - $250,200 PA

About the job

11 skills required for this role

Add these skills to join the top 1% applicants for this job

java

shell

bash

azure

python

perl

linux

fpga

communication

testing

test-coverage

Job Description

Microsoft's Silicon Engineering team seeks a Senior Product Engineer with 3+ years (or Master's + 3 years) experience in HPC/AI/GPU/CPU ATE test content (digital/analog), failure analysis, RMA execution, test hole resolution, ATE test bring-up, silicon characterization, and system-to-tester correlation. Responsibilities include developing and implementing technical solutions for ATE hardware and test programs for mixed-signal SOC devices, conducting system-level testing, developing automation scripts, writing test/characterization plans, creating project schedules, and communicating progress to teams. Strong problem-solving, statistical analysis, and debugging skills are crucial.

Must have:

3+ years ATE experience (Advantest 93K preferred)
Pre/post-silicon test engineering (analog, mixed-signal, HSIO, FPGA, SOC)
Failure analysis and fault isolation
Strong problem-solving and debugging skills
Automation scripting (Python, Java, Perl, etc.)

Good to have:

DFT experience
Semiconductor manufacturing flows
Cost reduction initiatives
EFA/PFA experience
Experience with cloud hardware

Perks:

Industry leading healthcare
Educational resources
Discounts on products and services
Savings and investments
Maternity and paternity leave
Generous time away
Giving programs
Networking opportunities

Overview

Microsoft is leading the way into the growth of High-Performance Computing and Artificial Intelligence. Recently Microsoft has announced Cobalt and Maia Custom Silicon for Azure Data Center and AI. Microsoft Silicon Engineering is pushing technology hard in all areas including advanced packaging technology. We are looking for a Senior Product Engineer with solid technical experience in the area of HPC/AI/GPU/CPU ATE Test Content (Digital and/or Analog), failure analysis and fault isolation, product RMA execution and dispositioning, test hole resolution, ATE test bring up, silicon characterization and system-to-tester correlation.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Qualifications

Required Qualifications:

Master's Degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field AND 5+ years technical engineering experience
- OR equivalent experience.
3+ years’ hands on experience in ATE usage, preferably Advantest 93K test platform, Pre and post silicon test engineering experience in analog mixed signal, HSIO, FPGA and SOC devices.

Other Requirements

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
- This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

Background in DFT - Design for Test techniques, product characterization.
Product manufactures manufacturing flows – Semiconductor manufacturing flows.
Background in cost reduction initiatives – Yield Improvement, test time reduction.
Software skills - scripting languages – Java, Perl, C or other relevant scripting language.
Outstanding problem solving, statistical analysis, and failure debug skills to root cause Silicon issues are required. Relevant experience in EFA and PFA – Electrical [E] & Physical [P] Failure Analysis [FA].
Presentation and communication skills – Cross functional teams and Senior management.
Statistical analysis.
Experience working with cloud hardware infrastructures and regression test execution.
Familiarity with additional scripting languages such as Shell or Bash

Electrical Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until February 17, 2025.

Responsibilities

You will develop and implement technical solutions for ATE hardware and test program with high quality for Mixed-signal, SOC type devices. You’ll also cross check silicon chip architecture, use performance instrumentation, and generate performance simulators and characterization reports.
Conduct system-level testing on both Linux and Windows platforms to ensure product robustness and reliability. Execute board bring-ups and driver installations for PCIe and various slow-speed I/O interfaces such as UART, I2C, I3C, and Ethernet protocols. Develop and maintain automation scripts using Python to streamline testing and integration processes.
You will write mixed-signal, SOC typde device test/characterization plan, test and guardband methodology.
You will create a single project implementation schedule and help determine resources needed for the hardware engineering of complex features or products. You’ll also identify significant project risks and communicate progress to internal and external teams.
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