Silicon Senior Physical Design Engineer, TPU
Job Summary
Job Description
- 7+ years experience in advanced design (clock/voltage domain crossing, DFT, low power)
- SoC experience
- High-performance, high-frequency, low-power design experience
- Define and implement physical design methodologies
- Manage timing and power consumption
- Master's degree in Electrical Engineering
- System Verilog and TCL scripting experience
- VLSI design in SoC or multiple SoC cycles in ASIC design
- Layout verification and design rules experience
1 skill required
Job Details
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 7 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
- Experience with System on a Chip (SoC) cycles.
- Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
- Master’s degree in Electrical Engineering.
- Experience in coding with System Verilog and scripting with TCL.
- Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.
- Experience with layout verification and design rules.
About the job
In this role, you will be part of a team developing cutting-edge SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define and drive the implementation of physical design methodologies.
- Take ownership of one or more physical design partitions or top level.
- Manage timing and power consumption of the design.
- Contribute to design methodology, libraries, and code review.
- Define the physical design related rule sets for the functional design engineers.
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