ASIC RTL Integration Engineer
Job Summary
Job Description
- 8+ years of experience in high-performance design
- Experience with Verilog or System Verilog
- Experience in multiple SoCs with silicon success
- Lead a team of ASIC RTL engineers
- Work with cross-functional teams
- Experience with ASIC design methodologies (Lint, CDC/RDC, Synthesis, DFT, UPF, Low Power Optimization)
- Knowledge of Process Cores, Interconnects, Debug, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 8 years of experience in high-performance design, multi-power domains with clocking.
- Experience in multiple SoCs with silicon success.
- Experience with Verilog or System Verilog language.
Preferred qualifications:
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software.
- Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features.
- Interact closely with architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and Performance, Power, Area (PPA) for sub-system/chip-level integration.
- Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
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