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Chassis Power Architect, Silicon

Karnataka, India (On-site)

Chassis Power Architect, Silicon

33 Minutes ago • 5 Years + • Research & Development

About the job

2 skills required for this role

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innovation

cross-functional

Job Description

The Chassis Power Architect, Silicon at Google will be part of a team developing custom silicon solutions for Google's direct-to-consumer products. Responsibilities include driving architecture and microarchitecture development for next-generation power management controllers, developing power optimization methods for various chassis IPs, influencing power methodology for SoC design and implementation, and developing innovative power optimization plans. The role also involves influencing generic power management IPs, guiding pre-silicon and post-silicon power correlation efforts, and interfacing with system and chipset power architects on power planning and management strategies. The focus is on next-generation power management controllers, chassis power architecture, and power vs. performance tradeoffs for various SoC and chassis components.

Must have:

Bachelor's degree in EE/CS or equivalent
5+ years power enhancement experience
Power management IP experience
Experience with UPF/CPF, multi-voltage domains
Verilog, SystemVerilog, RTL & SPICE simulation experience
EDA tools (Conformal LP, Power-Artist etc.) experience

Good to have:

Post-silicon power calibration and debug experience
Full chip power design and analysis experience
Understanding of clock, reset, and power sequencing

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in power enhancement workflow and techniques.
Experience with power management IPs.

Preferred qualifications:

Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
Experience in post-silicon power calibrations and debug.
Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Google Silicon Platform IP Architecture team, you will collaborate with SoC and IP hardware architects and Design Engineers to drive next generation power management controller and chassis power optimization in advanced technology nodes, focused on Google Tensor SoC and other associated products.

In this role, you will define power management controller and it’s deployment across SoC, power optimization methods, chart power roadmaps for Chassis IPs, propose power optimization plans in consultation with cross-functional teams, guide pre-silicon power modeling and post-silicon power correlation efforts, and interface with system and chipset power architects on both power planning and power management strategies. Your primary focus will be on our next-generation power management controller, chassis power architecture/microarchitecture and power vs performance tradeoffs for various SoC and chassis components.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment.
Come up with Power optimization methods for various chassis IP’s.
Influence Power methodology for design, verification and implementation of deep submicron SoCs.
Develop innovative plans to achieve power optimization from circuit to system level.
Influence generic power management IPs to drive clock, reset, and power controls.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.