CPU Design Manager, Hardware

1 Month ago • 8 Years + • Research & Development

Job Summary

Job Description

As a CPU Design Manager at Google, you will lead chip development projects from micro-architecture to implementation, ensuring quality, schedule, and performance targets (PPA). You'll coordinate various disciplines (design, verification, test) and collaborate with a leadership team to make execution decisions. Responsibilities include resolving technical issues, implementing best practices, and driving project development with high quality. You'll be part of a team creating custom silicon solutions powering Google's products. The role requires extensive experience with Verilog/SystemVerilog or VHDL, chip design flow, high-speed low-power design, and leading teams. You'll be accountable for the overall success of chip development projects, ensuring all specifications and requirements are met.
Must have:
  • 8+ years of experience in chip design
  • Expertise in Verilog/SystemVerilog or VHDL
  • Experience leading chip development projects
  • Strong understanding of chip architecture and design methodologies
  • High-speed, low-power design experience
Good to have:
  • Master's or PhD in Engineering
  • ASIC design methodology experience
  • Advanced high-performance CPU design knowledge
  • Excellent communication and leadership skills

Job Details


Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 8 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
  • Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
  • Experience working with high speed, lower power design.
  • Experience in leading chip development projects and teams.

Preferred qualifications:

  • Master's degree or PhD in Engineering.
  • Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
  • Knowledge of advanced high performance CPU design and architecture.
  • Ability to motivate and focus large collaborative teams to achieve testing goals.
  • Excellent communication and facilitation skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Own the chip development and execution. Be accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking.
  • Coordinate the work of different disciplines, such as design, verification, and test to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project - Technical Program Manager (TPM), design verification lead, Physical Design (PD) lead, Design for Testing lead, design lead and architecture team to make execution decisions and drive the development process.
  • Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
  • Lead the project development with excellent quality and address issues throughout the design and implementation phases.

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