Memory Controller Microarchitecture & Logic Design
Job Summary
Job Description
Rivos is building enterprise SOCs with leading performance, power, security, and RAS features. They are looking for Memory Controller and Logic Design experts to create high-performance memory interfaces. Responsibilities include microarchitecture development and specification, RTL design for power, performance, area, and timing goals, validation support, performance exploration, and working with multi-functional teams for physical design implementation.
Must have:
- Microarchitecture development and specification
- RTL design for power, performance, area, timing
- Validation and simulation support
- Performance exploration and correlation
- Logic design principles
- Low power microarchitecture techniques
- High performance techniques in memory controller microarchitecture
- Experience with SystemVerilog
- Experience with simulators and waveform debugging tools
- Experience with Perl or Python
Good to have:
- Memory controller or PHY design experience
- Experience with DDR, LPDDR, HBM memory technologies
4 skills required
Job Details
Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller and Logic Design experts to join our team in building the best high performance memory interface in the world.
Responsibilities
- Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
- Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
- Validation - support test bench development and simulation for functional and performance verification
- Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
- Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
Requirements
- Thorough knowledge of memory controller or PHY design and experience in one or more of the following memory technologies: DDR, LPDDR, HBM
- Knowledge of SystemVerilog
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture techniques
- Understanding of high performance techniques and trade-offs in memory controller microarchitecture
- Experience using an interpretive language such as Perl or Python
Education and Experience
- PhD, Master’s Degree, or Bachelor’s Degree in technical subject area
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