Multiple Openings in Bengaluru (onsite) HW DV, RTL Uarch, Performance Modeling

DAC Search Inc/Richard Goldstein specializes in Recruiting Services for Semiconductor, EDA, and Artificial Intelligence (AI) Chip companies, primarily startups

Feel free to review my webpage (www.richtherecruiter.com)

My client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team.

Positions Available in Bengaluru, India/fully onsite

1) RTL Microarchitect

We are hiring an experienced RTL Microarchitect with a passion for startups and the dynamic environment that comes with the territory and mindset.

The position is onsite in Bengaluru, India. Sorry there are no exceptions. The team is small and the cohesiveness of being together daily is paramount.

The experience we are looking for are "must haves", and can be a combination of skills listed below, namely CACHE COHERENCY, NOC, FABRIC, PIPELINING, INTERCONNECT

• Design and develop microarchitectures for a set of highly configurable IPs
• Microarchitecture and RTL coding ensuring optimal performance, power, area
• Collaborate with software teams to define configuration requirements, verification collaterals etc.
• Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications and Preferred Skills

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in microarchitecture and RTL development
• Proficiency in Verilog, System Verilog
• Familiarity with industry-standard EDA tools and methodologies
• Experience with large high-speed, pipelined, stateful designs, and low power designs
• In-depth understanding of on-chip interconnects and NoCs
• Experience with in ARM ACE/CHI or similar coherency protocols
• Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoCs
• Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
• Experience with modern programming languages like Python is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills

2) Design Verification Engineers

Design Verification engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Create test plans for highly configurable IPs meant to provide inter-connectivity between components across an SOC,chiplet or multi chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design teams test plans, failure debug, coverage etc.

3) Performance Architect

Seasoned Performance Architect with a strong background in performance modeling as well as architecture and microarchitecture analysis. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Work closely with architects and micro-architects to find innovative ways to develop performance models for different IP’s
• Develop system software in Python and C++
• Develop fabric and cache architecture models and data structures
• Develop core software optimization algorithms and platforms

Please apply for any of the openings here or email me directly (rich@dacsearch.com)