Silicon Subsystems RTL Design Engineer
Job Summary
Job Description
- 5+ years ASIC development experience
- Verilog/SystemVerilog, VHDL expertise
- ASIC design verification, synthesis, timing/power analysis, DFT
- Micro-architecture and subsystem design experience
- SoC design and integration flow experience
- Scripting languages (Python/Perl)
- High-performance/low-power design techniques
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
- Experience in micro-architecture and design of subsystems.
Preferred qualifications:
- Experience in SoC designs and integration flows.
- Experience with scripting languages (e.g., Python or Perl).
- Knowledge of high performance and low power design techniques.
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
You will be part of a team developing ASICs used to accelerate and improve traffic in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Own microarchitecture and implementation of subsystems in the data center domain.
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
- Perform Quality check flows like Lint, CDC, RDC, VCLP.
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Identify and drive power, performance and area improvements for the domains owned.
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