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Technology Manager, Analog/Mixed Signal IP, Silicon

California, United States (On-site)

Technology Manager, Analog/Mixed Signal IP, Silicon

6 Days ago • 8 Years + • Research & Development

About the job

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Job Description

This role involves being the technical expert responsible for Statement of Work (SOW) closure, ensuring specifications and milestones align with product priorities and schedules. Responsibilities include working with the team to provide specifications for building flows, implementing quality checks, and managing IP intake. You will map the IP ecosystem, plan future AMS IP requirements, and collaborate with Architecture, Product Management, Design, SOC IP Integration, and IP QA leads. Close collaboration with IP vendors is crucial for identifying new features, negotiating schedules, and influencing vendor IP portfolios to enhance Google product differentiation. You will drive SOWs and ECOs, manage version control, and develop IP QA checklists and guidelines. Ensuring IPs meet DFx, DV, software, testing, and characterization requirements by defining and specifying deliverables for analog IP is also key. The role includes managing vendor execution, delivery, schedules, issue resolution, and leading executive escalations and internal status reviews.

Must have:

8+ years analog mixed signal IP experience
SOC clocking, PLL, ADC design expertise
SOW closure and IP vendor management
Cross-functional collaboration
Defining deliverable requirements for analog IP

Good to have:

Experience with silicon IP vendors
SOC co-architecting with AMS IP (PLL) for PPA optimization
Knowledge of glitch, droop detectors, PVT monitors, and sensors
Familiarity with PCIe, USB, or LPDDR protocols

Perks:

Bonus
Equity
Benefits

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related field, or equivalent practical experience.
8 years of experience with analog mixed signal IP.
Experience in architecting SOC clocking, designing PLL, or ADC (analog to digital converter) A/D converters.

Preferred qualifications:

Experience in working with or managing silicon IP vendors.
Experience in co-architecting a SOC with AMS IP such as PLL to optimize PPA.
Experience working cross-functionally with domain experts from architecture, design, power.
Knowledge of glitch, droop detectors, PVT monitors and sensors.
Knowledge of PCIe, USB, or LPDDR protocols.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be the technical expert responsible for SOW closure, ensuring the specifications and milestones fit the product priorities and schedule. They will work with the team to provide specs to build flows for proper quality checks and IP intake.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Map the IP ecosystem, plan, and anticipate future AMS IP product requirements.
Work with Architecture, Product Management, Design and SOC IP Integration, and IP QA leads to ensure future product quality.
Work closely with IP vendors to identify new features, negotiate schedules, influence vendor IP portfolio to maximize Google product differentiation. Drive SOW and ECOs, change and version controls, and develop IP QA checklists and guidelines.
Ensure that the IPs are meeting our DFx, DV, software, testing, and characterization requirements by defining and specifying deliverable requirements for analog IP.
Manage vendor execution, delivery, schedules and issue resolution, lead executive escalation and internal status reviews.

View Full Job Description

$150.0K - $223.0K/yr (Outscal est.)

$186.5K/yr avg.

Mountain View, California, United States

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.